1. Field of the Invention
The present invention relates generally to the synchronization of asynchronous data and, more particularly, to a low latency method of synchronizing high-speed asynchronous data.
2. Background of the Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
In many computing systems, communications are transmitted between various interconnected devices. These devices may include processing devices coupled together via a host communication medium, as well as input/output (I/O) devices coupled together via an I/O communication medium. Each of these devices generally includes a core clock which provides the timing reference for internal data processing logic. Accordingly, communications internal to each device are referenced to the device""s core clock. Further, each of the devices in a computing system may be configured to generate and transmit communications to other devices in the computing system. Such communications, also may be referenced to the transmitting device""s core clock.
Devices in the computing system may be configured to operate in either a synchronous data communication mode or an asynchronous data communication mode. In the synchronous mode, the core clocks of the transmitting and receiving devices are derived from a common time base. Thus, the transmission and receipt of data is synchronous to the common time base, although the core clocks in the transmitting and receiving devices may have different frequencies. In the synchronous mode, no special provisions for ensuring accurate receipt and sampling of data in the receiving device are provided.
In the asynchronous mode, the core clock in the transmitting device is not derived from the same time base source as the core clock in the receiving device. As a result of the different time bases, the data may not be received and sampled accurately in the receiving device because the behavior of the data sampling logic may be unpredictable due to metastability effects. To address this problem, the transmitted data is synchronized to the core clock in the receiving device as the data propagates from the transmitting clock domain to the receiving clock domain.
Data synchronization may be accomplished by delaying the data as it propagates to the receiving clock domain. In some computing systems, the delay may be implemented by routing the data through, for example, a series of buffers (e.g., flip-flop devices) clocked by the receiving clock. The number of buffers connected in series determines the amount of the propagation delay. The longer the delay, the greater the probability that unpredictable behavior (i.e., metastability) will not occur and that the data may be accurately sampled when received into the receiving clock domain.
Although this approach to data synchronization may reduce the probability of data sampling errors due to metastability, it does so at the cost of delaying the receipt of synchronized data in the receiving clock domain. As computing systems operate at progressively higher frequencies, more stages of buffering are required and the data latency incurred as a result of the synchronization process becomes more relevant. Accordingly, it would be desirable to provide a data synchronization scheme that substantially reduces the probability of errors due to metastability, yet also substantially reduces or obscures the latency that otherwise may be incurred by the synchronization of the data.
The present invention may be directed to one or more of the problems set forth above.
Certain aspects commensurate in scope with the originally claimed invention are set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of certain forms the invention might take and that these aspects are not intended to limit the scope of the invention. Indeed, the invention may encompass a variety of aspects that may not be set forth below.
In accordance with one aspect of the present invention, there is provided a method of synchronizing data to a receiving clock in a receiving clock domain. The method comprises the acts of receiving a communication that is referenced to a transmitting clock asynchronous to the receiving clock and which includes data and a synchronization signal. The synchronization signal is synchronized to the receiving clock. A load pointer for loading data into a buffer synchronous with the transmitting clock is reset in response to receipt of the synchronization signal. An unload pointer for unloading data from the buffer synchronous with the receiving clock is reset in response to the completion of the synchronizing of the synchronization signal. The unload pointer also is offset by an initial offset corresponding to an amount of data loaded into the buffer during the synchronizing of the synchronization signal.
In accordance with another aspect of the present invention, there is provided a method of synchronizing data to a receiving clock in a receiving clock domain. The method comprises receiving a communication referenced to a transmitting clock that is asynchronous with the receiving clock. The communication includes data and a synchronization signal. A load pointer for loading data into a buffer synchronous with the transmitting clock is reset in response to receipt of the synchronization signal. To synchronize the synchronization signal to the receiving clock, the propagation of the synchronization signal into the receiving clock domain is delayed. An unload position for an unload pointer, which unloads data from the buffer synchronous with the receiving clock, is determined in response to completion of the synchronization of the synchronization signal. The unload position compensates for the synchronization delay.
In accordance with still another aspect of the present invention, there is provided a device for use in a computing system. The device comprises a core clock and a receive port configured to receive a communication referenced to a transmitting clock that is asynchronous with the core clock. The communication comprises data and a synchronization signal. The receive port comprises a synchronizer to receive the synchronization signal and synchronize it to the core clock, a buffer, a load pointer for loading; data into the buffer synchronous with the transmitting clock, and an unload buffer for unloading data from the buffer synchronous with the core clock. The receive port also comprises unload pointer offset logic in communication with the synchronizer and the unload pointer. The load pointer is reset to a reset position in response to receipt of the synchronization signal by the synchronizer. The unload pointer offset logic is configured to determine an offset amount of the unload pointer from the reset position in response to synchronization of the synchronization signal.